Polysilicon resistors have been frequently used in conventional integrated circuit (IC) design. Likewise, due to shrinking technology nodes, high-k dielectric material and metal are often considered to form a gate stack for a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET). However, various integration issues exist when combining polysilicon resistors and metal-gate MOSFETs onto a single IC chip. One solution is to utilize a dummy gate when forming a polysilicon resistor. A gate replacement process, such as an etch process, can then be implemented to remove the dummy gate. However, the formed polysilicon resistors can be damaged and recessed by the etch process, causing the deviation of the resistance of the polysilicon resistor from the designed target and other problems. A solution to this problem is to deposit the polysilicon resistor at the same time of depositing the dummy gate and covering the polysilicon resistor with a hard mask during implantation of the of the source/drain regions and/or during formation of the dummy gate replacement. However, this causes a need for an extra hard mask deposition, which in-turn adds complexity and cost to the fabrication process. Therefore, an improved polysilicon resistor structure and a method making are needed to address the above issues.